Digital circuits employing CMOS (Complementary Metal Oxide Semiconductor) technology may consume a small enough current during the static or off state that they may be effectively ignored. Thus, CMOS digital circuits having a relatively low power consumption have been used in mobile devices. Likewise, input/output circuits may benefit from having a level shifter circuit whose power consumption is relatively low.
A level shifter circuit having a current mirror configuration may generate a non-negligible amount of leakage current during the static or “off” state. For example, a level shifter circuit is disclosed in Japanese Patent Application Publication Number JP07-086913. While the leakage current of the level shifter circuit disclosed in Japanese Patent Application Publication Number JP07-086913 may be reduced, such a circuit may nevertheless generate a non-negligible leakage current.
FIG. 1 is a circuit diagram illustrating a conventional level shifter circuit, and FIG. 2 is a timing diagram showing voltage waveforms of input signals, output signals and nodes for the circuit shown in FIG. 1.
Referring to FIG. 1, an input buffer 10 includes a two-stage inverter and generates a first input signal (node N11) that is inverted with respect to a preliminary input signal at node N10, and a second input signal (node N12) that is inverted with respect to the first input signal at node N11.
The first input signal (node N11) is provided to a first switching circuit 11, and the second input signal is provided to a second switching circuit 12. The first switching circuit 11 and the second switching circuit 12 may include a first NMOS transistor MN11 and a second NMOS transistor MN12, respectively, which may function as switching transistors.
A level control circuit 13 includes a first PMOS transistor MP11 and a second PMOS transistor MP12 connected in a current mirror configuration. The first PMOS transistor MP11 and the second PMOS transistor MP12 may function as current supply transistors in the current mirror.
A third PMOS transistor MP31 located between the first NMOS transistor MN11 and the first PMOS transistor MP11 may be turned off in order to shut off a constant current flow following a predetermined delay after the first NMOS transistor MN11 is turned on.
An output terminal (node N15) coupled to a junction of the second NMOS transistor MN12 and the second PMOS transistor MP12 outputs a first output signal.
The first output signal passes through an output buffer 20 including serial inverters to generate a final output signal i.e., a second output signal at a node N16.
Referring to FIG. 2, at the outset of the timing diagram (i.e. in the “B” region), the first input signal of node N11 has a high level, the second input signal at node N12 has a low level, and the second output signal at node N16 has a high level.
At this time, the first NMOS transistor MN11 is in the on-state, and the second NMOS transistor MN12 is in the off-state. Because the second output signal (node N16) has a high level, the third PMOS transistor MP31 assumes an off-state. Thus, the flow of current from the current mirror 13 to the first NMOS transistor MN11 is blocked.
Because the first NMOS transistor MN11 is in an on-state in the B-region as shown in FIG. 2, the drain (node N14) of the NMOS transistor MN11 assumes a low level.
Because the third PMOS transistor MP31 is in the off-state, the drain (node N13) of the first PMOS transistor MP11 assumes a high level. However, the maximum voltage on the drain of the first PMOS transistor MP11 is not the power supply voltage VDD2. Rather, the maximum voltage of the drain of the first PMOS transistor MP11 is equal to the supply voltage VDD2 less the PMOS threshold voltage (VDD2−Vthp).
The reduced voltage (VDD2−Vthp) is applied to the gate of the second PMOS transistor MP12, causing the second PMOS transistor MP12 to be in an off-state.
Because the second NMOS transistor MN12 is in the off-state, the first output signal of the output terminal N15 has a high level, and the second output signal (node N16) outputted from the output buffer 20 accordingly has a high level.
However, the first output signal at terminal node N15 may not maintain its high level due to a difference between leakage currents of the second NMOS transistor MN12 and the second PMOS transistor MP12. In particular, if the leakage current of the second NMOS transistor MN12 is larger than the leakage current of the second PMOS transistor MP12, the first output signal at node N15, initially having a high level, may decrease from the supply voltage VDD2, and the leakage current of the fourth PMOS transistor MP21, which forms part of the first inverter of the output buffer 20, may increase to a significantly large value.
If the first output signal at node N15 having a high level is lower than the threshold voltage of the fourth PMOS transistor MP21, the third NMOS transistor MN21 and the fourth PMOS transistor MP21 forming the first inverter of the output buffer 20 may both be turned on or partially on, thereby permitting a relatively large leakage current to flow therethrough.
Accordingly, when the first input signal (node N11) has a high level and the second input signal (node N12) has a low level (i.e. in the B region), it may be desirable to maintain the first output signal at the high level (VDD2) in order to reduce leakage currents.
As shown in FIG. 2, when the first input signal at node N11 is changed to a low level from a high level, the first NMOS transistor MN11 is turned off and the second NMOS transistor MN12 is turned on. Because the second NMOS transistor MN12 is turned on, the first output signal at node N11 is changed to a low level and the output buffer 20 outputs a low level as the second output signal after a predetermined switching delay.
The gate of the third PMOS transistor MP31 is coupled to the second output signal. Thus, when the second output signal switches to a low level, the third PMOS transistor MP31 is turned on and the drain voltage of the first NMOS transistor MN11 (node N14) is pulled-up to the reduced voltage level (VDD2−Vthp).
At the same time, the drain voltage of the first PMOS transistor MP11 (node N13) temporarily falls from the reduced voltage level (VDD2−Vthp) and rises again to the reduced voltage level (VDD2−Vthp).
If the drain voltage of the first PMOS transistor MP11 (node N13) is slightly larger than the reduced voltage level (VDD2−Vthp), the first PMOS transistor MP11 will be automatically turned off. Thus, it may be difficult or impossible for the drain voltage of the first PMOS transistor MP11 to rise to a voltage level larger than or equal to the reduced voltage level (VDD2−Vthp).
Additionally, the gate of the first PMOS transistor MP11 and the gate of the second PMOS transistor MP12, which are commonly coupled to the drain of the first PMOS transistor MP11, have the voltage level (VDD2−Vthp). As a result, the gate voltage of the second PMOS transistor MP12 has the voltage level (VDD2−Vthp), which is lower than the voltage level VDD2. Thus, the second PMOS transistor MP12 may not be completely turned off, which may result in the fist PMOS transistor MP11 having a relatively large leakage current.
When the second PMOS transistor MP12 is at the sub-threshold voltage level, the second PMOS transistor MP12 may generate a leakage current similar to the relatively large leakage current described above.
If the threshold voltage of the second PMOS transistor MP12 is lower than the threshold voltage of the first PMOS transistor MP11, the second PMOS transistor MP12 may experience a leakage current proportional to the square of the difference between the threshold voltages of the first PMOS transistor MP11 and the second PMOS transistor MP12.
In sum, when the first output signal (node N15) has a high level, it may be desirable to continuously maintain the first output signal (node N15) at the high level so that leakage current from the output buffer 20 may be reduced.
Additionally, when the first output signal has a low level, it may be desirable to reduce leakage current from the second PMOS transistor MP12.